Many types of semiconductor memories, including static random access memories (SRAMs), dynamic random access memories (DRAMs), FIFOs, dual-port memories, and read-only memories of various types, fabricated as individual components and embedded in other integrated circuits such as microprocessors and other logic devices, are containing greater numbers of storage locations, and higher capacity, as the manufacturing technology improves. For example, SRAMs having 2.sup.20 storage locations (i.e., 1 Mbits) and DRAMs having 2.sup.22 storage locations (i.e., 4 Mbits) are available in the market.
For the general commercial market, such a memory is usable only if each and every storage location can be accessed and can store both digital data states. Failure of a single storage location, or bit, thus causes the entire memory (and logic device having an embedded memory) to be non-salable. Considering the relatively large chip size and high manufacturing costs for the high density memories noted hereinabove, such memories are particularly vulnerable to the effect of extremely small (in some cases sub-micron) defects that cause single "stuck" bits.
As a result, many semiconductor memories are now fabricated with so-called redundant storage locations, which are enabled in the event of defects in the primary memory array. For ease of enabling, and also to address row or column defects, the redundant storage locations are generally formed as redundant rows or columns which, when enabled, replace an entire row or column of the primary memory array. The enabling of such redundant storage location is conventionally done during the manufacturing test process, where the primary memory is tested for functionality of the bits therein. The addresses of failing bits are logged, and an algorithm in the automated test equipment determines if the redundant rows or columns available on the circuit are sufficient to replace all of the failing bits. If so, fuses are opened (or, alternatively, anti-fuses may be closed) in the decoding circuitry of the memory so that the failing row or column is no longer enabled by its associated address value, and so that a redundant row or column is enabled by the address associated with the failing row or column. Examples of memory devices incorporating conventional redundancy schemes are described in Hardee, et al., "A Fault-Tolerant 30 ns/375 mW 16K.times.1 NMOS Static RAM", J. Solid State Circuits, Vol. SC-16, No. 5 (IEEE, 1981), pp. 435-43, and in Childs, et al., "An 18 ns 4K.times.4 CMOS SRAM", J. Solid State Circuits, Vol. SC-19, No. 5 (IEEE, 1984), pp. 545-51.
A major constraint in the design of a memory with redundancy is the chip area required to incorporate the redundant elements and associated decode circuitry. The choice of the number and arrangement of redundant elements depends upon a number of factors. The primary tradeoff is the cost of chip area versus the benefit of repairing otherwise failing devices. Based upon the types of defects (i.e., those which cause failing rows, those which cause failing columns, those which cause failing isolated bits, and those which cause the entire array to fail) and their expected frequency over the product life cycle, the tradeoff of number and arrangement of redundant cells versus chip area can be made.
Multiple input/output memories provide special problems in the implementation of redundant storage cells, as the redundant storage cells must be somehow associated with the various input/outputs. In memories which have the primary memory array arranged in multiple blocks, or sub-arrays, so that power dissipation can be reduced by selecting only one of the sub-arrays rather than the entire memory, all input/output terminals must be in communication with each of the sub-arrays. In prior memories so arranged, redundant elements, particularly columns, have been relatively inefficient as the same number of columns as input/output terminals have been associated with each sub-array or block, with each redundant column dedicated to one of the input/output terminals. As such, enabling of the redundant elements has required enabling of more redundant columns that may otherwise be necessary; furthermore, if a sub-array or block has failing cells associated with more than one column address, either two entire sets of columns must be provided, or else the memory cannot be repaired. It should be noted that with the number of input/output terminals increasing (with by-eight memories being commonplace), and with the number of storage cells in a memory becoming higher over time (with 1 Mbit SRAMs and 4 Mbit DRAMs being commonplace) such that segmentation of the memory array becomes more desirable from a power dissipation standpoint, dedication of redundant columns to individual input/output terminals becomes even more expensive from a chip area standpoint.
It is therefore an object of this invention to provide a memory having improved efficiency of use of redundant storage cells.
It is a further object of this invention to provide such a memory useful with multiple input/output terminals.
It is a further object of this invention to provide such a memory which includes a plurality of sub-arrays.
It is a further object of this invention to provide such a memory which has redundant storage cells associated with each of a plurality of sub-arrays.